收藏本站
ADuC7060
SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
SPISTA Register
Name:
Address:
Default value:
Access:
Function:
SPISTA
0xFFFF0A00
0x00000000
Read only
This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
Table 104. SPISTA MMR Bit Designations
Bit
15:12
11
10:8
7
6
5
4
3:1
0
Name
SPIREX
SPIRXFSTA[2:0]
SPIFOF
SPIRXIRQ
SPITXIRQ
SPITXUF
SPITXFSTA[2:0]
SPIISTA
Description
Reserved bits.
SPI receive FIFO excess bytes present. This bit is set when there are more bytes in the receive FIFO than
indicated in the SPIRXMDE bits in SPICON.
This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIRXMDE.
SPI receive FIFO status bits.
[000] = receive FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
SPI receive FIFO overflow status bit.
Set when the receive FIFO was already full when new data was loaded to the FIFO. This bit generates an
interrupt except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI receive IRQ status bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes have been received.
Cleared when the SPISTA register is read.
SPI transmit IRQ status bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes have been transmitted.
Cleared when the SPISTA register is read.
SPI transmit FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the transmit FIFO. This bit generates an
interrupt except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI transmit FIFO status bits.
[000] = transmit FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
SPI interrupt status bit.
Set to 1 when an SPI based interrupt occurs.
Cleared after reading SPISTA.
Rev. 0 | Page 92 of 100
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
EVAL-ADUC845QSPZ KIT DEV QUICK START ADUC845
EVAL-ADUM3070EBZ BOARD EVAL FOR ADUM3070
EVAL-SDP-CB1Z BOARD EVALUATION FOR SDP-CB1
EVB51JM128 BOARD EVAL FOR MCF51JM128 MCU
EVBQE128 BOARD EVAL FLEXIS QE128 FAMILY
F2068 PNL FIBERGLASS 18.44X14.44" WHT
FAN3100CMPX IC GATE DRVR SGL CMOS 2A 6MLP
FAN3111CSX IC GATE DVR 1CH 1A LOW SOT23-5
相关代理商/技术参数
EVAL-ADUC7060QSPZU1 制造商:Analog Devices 功能描述:
EVALADUC7060QSPZU2 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits)
EVAL-ADUC7061MKZ 功能描述:开发板和工具包 - ARM Quick Start Development System RoHS:否 制造商:Arduino 产品:Development Boards 工具用于评估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口类型:DAC, ICSP, JTAG, UART, USB 工作电源电压:3.3 V
EVAL-ADUC7061MKZ 制造商:Analog Devices 功能描述:ADUC7061MKZ EvaluationBoard
EVAL-ADUC7061MKZU2 制造商:Analog Devices 功能描述:PN may be NE CE 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD - Boxed Product (Development Kits)
EVAL-ADUC7121QSPZ 功能描述:BOARD EVALUATION FOR ADUC7121 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:MicroConverter® ADuC7xxx 标准包装:1 系列:PICDEM™ 类型:MCU 适用于相关产品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，线缆，元件，CD，PICkit 编程器 产品目录页面:659 (CN2011-ZH PDF)
EVALADUC7121QSPZU1 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Boxed Product (Development Kits)
EVAL-ADUC7122QSPZ 功能描述:BOARD EVALUATION FOR ADUC7122 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:MicroConverter® ADuC7xxx 标准包装:1 系列:PICDEM™ 类型:MCU 适用于相关产品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，线缆，元件，CD，PICkit 编程器 产品目录页面:659 (CN2011-ZH PDF)